# fpga.chat full AI context

## Summary

fpga.chat is a verified AI assistant and workflow platform for FPGA/EDA debugging. It helps FPGA engineers, students and embedded teams understand EDA tool errors, analyze HDL/project artifacts, and produce evidence-backed reports. The product is currently Private Alpha — Under Construction.

The first MVP focus is EDA Error Decoder for FPGA tool logs from Vivado, Quartus, Gowin EDA, Yosys and Verilator.

## Public landing copy

H1: fpga.chat — verified AI assistant for FPGA/EDA debugging.

Subtitle: Paste Vivado, Quartus, Gowin, Yosys or Verilator logs. Get root-cause hypotheses, evidence, source-backed explanations, limitations and reproducible next steps.

Status: Private Alpha · Under Construction.

Current explanation: We are building fpga.chat in public. The first version focuses on EDA Error Decoder for FPGA tool logs. Join early access or send an example log to help shape the MVP.

## Problem

- EDA logs are verbose and vendor-specific.
- Beginners do not know which message matters.
- Experienced engineers lose time mapping errors to docs, constraints, build scripts and board facts.
- Generic chatbots can hallucinate fixes, pinouts and tool behavior.

## Solution

fpga.chat is not another chatbot. It is intended to be a verified FPGA workflow layer.

Pipeline:

1. Artifact input.
2. Local/browser precheck.
3. Redaction.
4. Deterministic log/HDL/constraint parsing.
5. RAG with provenance.
6. Rule-based diagnosis.
7. LLM explanation synthesis.
8. Structured report.
9. CI/IDE/export.

Core principle: LLM output is not the source of truth. The system should combine deterministic parsing, redaction, retrieval with provenance, rule-based diagnosis, tool outputs and structured reports.

Every future engineering answer/report should expose:

- confidence;
- evidence;
- sources;
- tool_results;
- warnings;
- limitations;
- repro_steps;
- next_actions.

## MVP workflows

### EDA Error Decoder

- Decode Vivado, Quartus, Gowin, Yosys and Verilator logs.
- Detect tool, stage, error IDs and likely root cause.
- Return evidence, sources and next command.

### FPGA Project Doctor

- Upload a project archive.
- Detect file tree, HDL graph, missing includes, constraints and build issues.
- Public cloud runs open-source checks only.

### Verified Testbench Generator

- Generate cocotb or SystemVerilog testbench drafts.
- Mark output as draft unless simulator run succeeds.

### Board Starter / Pinout Checks

- Board facts must be source-backed and revision-scoped.
- No generated pinouts from model memory.

### CI/API Checker

- JSON, SARIF and JUnit reports.
- GitHub Action, GitLab CI and VS Code integration later.

## How it works

1. Paste or upload an EDA log.
2. Secrets and local paths are redacted.
3. Parsers detect tool, stage and error patterns.
4. Retrieval finds source-backed documentation snippets.
5. Report shows evidence, confidence, limitations and next actions.

## Trust and safety

Your uploads are not used to train or fine-tune models by default.

Public-cloud fpga.chat will not run Vivado, Quartus or Gowin vendor tools by default. Vendor tool execution is planned through a local connector or enterprise/on-prem deployment.

Generated HDL, constraints and testbenches are drafts unless the report includes successful tool execution.

fpga.chat does not claim timing, CDC or RDC signoff.

Private and enterprise modes are planned.

## Target users

- Students and beginners.
- FPGA makers.
- RTL/FPGA engineers.
- Embedded teams.
- CI/DevOps engineers.
- Enterprise/on-prem users.

## Roadmap

### Now

- landing page;
- early access collection;
- EDA Error Decoder design;
- seed error corpus.

### Next

- log parser MVP;
- report viewer;
- RAG corpus;
- first API;
- VS Code and CI prototypes.

### Later

- Project Doctor;
- local vendor connector;
- team workspaces;
- private corpora;
- enterprise/on-prem package.

## API overview

The public API is planned. The intended output shape is structured, machine-readable reports rather than unconstrained chat text. Planned report fields include confidence, evidence, sources, tool_results, warnings, limitations, repro_steps and next_actions. Until the API is published, use the documentation and product manifest as the stable machine-readable public surface.

## Important URLs

- Landing: https://fpga.chat/
- Technical overview: https://fpga.chat/docs/overview.md
- Roadmap: https://fpga.chat/docs/roadmap.md
- Security and privacy stance: https://fpga.chat/docs/security.md
- API overview: https://fpga.chat/docs/api.md
- Limitations: https://fpga.chat/docs/limitations.md
- Product manifest: https://fpga.chat/product.json
- Concise AI context: https://fpga.chat/llms.txt
- Early access/contact: mailto:help@fpga.chat?subject=fpga.chat%20early%20access