# fpga.chat

> fpga.chat is a verified AI assistant and workflow platform for FPGA/EDA debugging. It is currently under construction and focused first on EDA Error Decoder for Vivado, Quartus, Gowin, Yosys and Verilator logs.

## Status

Private Alpha — Under Construction.

## Target users

- FPGA engineers.
- RTL and embedded teams.
- Students and beginners.
- FPGA makers.
- CI/DevOps engineers working with hardware builds.
- Enterprise/on-prem users who need private workflows.

## What it does

- Explains FPGA/EDA tool logs.
- Produces evidence-backed reports.
- Shows confidence, limitations and reproducible next steps.
- Does not treat LLM output as the source of truth.

## Core workflows

- EDA Error Decoder.
- FPGA Project Doctor.
- Verified Testbench Generator.
- Board Starter / Pinout Checks.
- CI/API Checker.

## MVP scope

The first MVP is EDA Error Decoder for Vivado, Quartus, Gowin EDA, Yosys and Verilator logs.

## Limitations

- No timing signoff.
- No CDC/RDC signoff.
- No unsourced pinout generation.
- No cloud execution of Vivado, Quartus or Gowin vendor tools by default.
- User uploads are not used for model training by default.
- Product is under construction and should not be described as generally available.

## Important URLs

- Landing: https://fpga.chat/
- Technical overview: https://fpga.chat/docs/overview.md
- Roadmap: https://fpga.chat/docs/roadmap.md
- Security and privacy stance: https://fpga.chat/docs/security.md
- API overview: https://fpga.chat/docs/api.md
- Limitations: https://fpga.chat/docs/limitations.md
- Product manifest: https://fpga.chat/product.json
- Full AI context: https://fpga.chat/llms-full.txt
- Early access/contact: mailto:help@fpga.chat?subject=fpga.chat%20early%20access