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UART Control Lite

Reusable open control-plane ingress core for lightweight board bring-up commands, runtime configuration, and client command bridging.

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Compatibility

Build schema present

  • Can be reviewed for Build graph integration
  • AccelFury af compatibility review needed
  • No automatic promotion into Build without review.
Core ID
uart-control-lite
Version
0.1.0
License
Apache-2.0
Pricing
Free
Language
systemverilog
Top module
uart_control_lite
Interfaces

Connection hints

  • control: uart, registers, telemetry

Clock domains: clk_i (data)

Usage contract

Free listing

Gross
$0.00
Creator share
$0.00
Platform fee
20%
Credits
0

Paid core usage is recorded when a paid Build export or private Build job includes the core version.

Variants

Resource evidence

  • default: LUT 0, FF 0, BRAM 0 kbit.

Values are catalog estimates until backed by synthesis and place-and-route evidence.

Review gate

What is missing

  • Estimated resources are not synthesis evidence.
  • No timing, CDC or RDC signoff is implied.
  • AccelFury af compatibility must be reviewed before promotion.
Evidence

Sources

fpga-skillls IP catalog: UART Control Lite

catalog_api

library/ip/catalog/uart-control-lite-frameworkseed-38d96e81.json

fpga-skillls payload: uart_control_lite.sv

test_artifact

library/ip/sources/public/framework-seed/uart-control-lite/rtl/uart_control_lite.sv
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