Trust and limits
Limitations
Hard boundaries for signoff, pinouts, vendor tools, generated artifacts and hardware review.
Use when
- You need a quick list of what fpga.chat must not be treated as.
- You are preparing documentation, integration copy or an AI-agent prompt.
- You want to check whether a proposed claim is too strong for public alpha.
Outcome
- Production, signoff and unsourced-board claims are avoided.
- Constructor language stays planned/alpha instead of current production scope.
- Hardware review responsibility remains explicit.
Hard boundaries
- Not generally available.
- Not a timing, CDC or RDC signoff authority.
- No pinouts generated from model memory.
- Board facts must be source-backed and revision-scoped.
- No public-cloud Vivado, Quartus or Gowin execution by default.
- Generated artifacts are drafts unless verified by successful tool output.
Interpretation rule
- Describe fpga.chat as a private-alpha FPGA/EDA developer tool.
- Describe the constructor as planned and under construction.
- Do not describe the service as production, a signoff system or an unsourced board database.